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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 preliminary information rev. 00c 07/22/02 is71v08f64gs08 is71v16f64gs08 issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. preliminary information july 2002 3.0 volt-only flash & sram combo with stacked multi-chip package (mcp) ? 64 mbit simultaneous operation flash memory and 8 mbit static ram mcp features ? power supply voltage 2.7v to 3.3v high performance: flash: 70 ns maximum access time sram: 70 ns maximum access time package: 101-ball bga & 73-ball bga industrial temperature: -40c to +85c flash features power dissipation: read current at 1 mhz: 7 ma maximum read current at 5 mhz: 18 ma maximum sleep mode: 5 a maximum simultaneous r/w operations (dual virtual bank): zero latency between read and write operations; data can be programmed or erased in one bank while data is simultaneously being read from the other bank low-power mode: a period of no activity causes flash to enter a low-power state erase suspend/resume: suspends of erase activity to allow a read in the same bank sector erase architecture: 16 words of 4k size and 126 words of 32k size (32 mbit) any combination of sectors, or the entire flash can be simultaneously erased erase algorithms: automatically preprograms/erases the flash memory entirely, or by sector program algorithms: automatically writes and verifies data at specified address hidden rom region: 256 byte with a factory-serialized secure electronic serial number (esn), which is accessible through a command sequence data polling and toggle bit: allow for detection of program or erase cycle completion ready-busy output (ry/ by ) detection of program or erase cycle completion over 100,000 write/erase cycles low supply voltage (vccf 2.5v) inhibits writes wp /acc input pin: if v il , allows partial protection of boot sectors if v ih , allows removal of boot sector protection if vacc, program time is improved sram features (8 mb density) power dissipation: operating: 25 ma maximum standby: 15 a maximum chip selects: ce1 s, ce2s power down feature using ce1 s, or ce2s, or lb s & ub s data retention supply voltage: 1.0 to 3.3 volt byte data control: lb s (dq0?dq7), ub s (dq8?dq15) ? on x16 version general description the flash and sram mcp is available in 64 mbit flash/8 mbit sram, with a data bus of either x8 or x16. the 64 mbit flash is composed of 4,194,304 words of 16 bits or 8,388,608 bytes of 8 bits. the 8mbit sram has 524,288 words of 16 bits or 1,048,576 bytes of 8 bits. data lines dq0-dq7 handle the x8 format, while lines dq0-dq15 handle the x16 format. the package uses a 3.0v power supply for all operations. no other source is required for program and erase opera- tions. the flash can be programmed in system using this 3.0v supply, or can be programmed in a standard eprom programmer. the 64 mbit flash/8 mbit sram is offered in a 73-ball bga or 101-ball bga package. the flash is compatible with the jedec flash command set standard. the flash access time is 70 or 85 ns and the sram access time is 70 ns. the flash architecture is composed of two virtual banks made of a combination of four physical banks, which allows simultaneous operation on each. optimized per- formance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. both operations would then be operating simultaneously, with zero latency.
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? logic symbol mcp block diagram gnd gnd v cc f ry/ by 8-mbit static ram 64-mbit flash memory dq0-dq15/a-1 a0-a21 a0-a21 a-1 wp /acc reset ce f i/of sa lb s ub s we oe ce1 s ce2s dq0-dq15 a0-a18 v cc s a0-a21,a-1 sa ce f ce1 s ce2s oe we wp /acc reset ub s lb s i/of dq0-dq15 23 ry/ by x16 or x8
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash memory block diagram state control & command register reset we ce byte wp /acc dq0-dq15 a0-a19 a0-a19 a0-a19 a0-a19 a0-a19 lower bank address upper bank address y -decoder latches and control logic lower bank upper bank x-decoder y -decoder latches and control logic x-decoder status control dq0-dq15 dq0-dq15 dq0-dq15 oe byte oe byte v cc gnd ry/ by flash bank organization physical bank bank size number of sectors sector size 1 8mb 8 8kb / 4kw 15 64kb / 32kw 2 24mb 48 64kb / 32kw 3 24mb 48 64kb / 32kw 4 8mb 15 64kb / 32kw 8 8kb / 4kw note : groups of banks can be configured into two virtual banks.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 pin descriptions a0-a18 address inputs, common a19-a21, a-1 address inputs, flash dq0-dq15/a-1 data inputs/outputs reset reset ce1 s, ce2s chip selects, sram i/of i/o configuration, flash ce f chip enable input, flash oe output enable input we write enable input lb s lower-byte control (dq0-dq7), sram ub s upper-byte control (dq8-dq15), sram wp /acc write protect/acceleration pin, flash ry/ by ready/busy output sa high order address pin, sram (x8) nc no connection vccf power, flash vccs power, sram gnd ground 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 pin configuration (64 mb flash and 8 mb sram) 73 ball fbga (top view) 12345678910 anc nc bncncncnc cnc a7 lb wp /acc we a8 a11 da3a6 ub reset ce2s a19 a12 a15 e a2 a5 a18 ry/ by a20 a9 a13 a21 f nc a1 a4 a17 a10 a14 nc nc g nc a0 gnd dq1 dq6 sa a16 nc h ce f oe dq9 dq3 dq4 dq13 dq15/a-1 i/of j ce1 s dq0 dq10 v cc fv cc s dq12 dq7 gnd k dq8 dq2 dq11 nc dq5 dq14 lncncncnc mnc nc 1234 1 23 4 1 23 4 1234 shared flash only sram only
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? pin descriptions a0-a18 address inputs, common a19-a21, a-1 address inputs, flash dq0-dq15/a-1 data inputs/outputs reset reset ce1 s, ce2s chip selects, sram i/of i/o configuration, flash ce f chip enable input, flash oe output enable input we write enable input lb s lower-byte control (dq0-dq7), sram ub s upper-byte control (dq8-dq15), sram wp /acc write protect/acceleration pin, flash ry/ by ready/busy output, flash sa address input pin, sram (x8) nc no connection vccf power, flash vccs power, sram gnd ground 1234 1 23 4 1 23 4 1234 shared flash only sram only 123456789012 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 123456789012 1234567890123 1 23456789012 3 1 23456789012 3 1 23456789012 3 1 23456789012 3 1234567890123 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 123456789012 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 123456789012 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 pin configuration (64 mb flash and 8 mb sram) 101 ball fbga (top view) 123456789101112 ancncnc ncncnc bncncnc ncncnc cncncnc ncnc ncncnc dnc a7 lb s wp /acc we a8 a11 ea3a6 ub s reset ce2s a19 a12 a15 f a2 a5 a18 ry/ by a20 a9 a13 a21 g nc a1 a4 a17 a10 a14 nc nc h nc a0 gnd dq1 dq6 sa a16 nc j ce f oe dq9 dq3 dq4 dq13 dq15/a-1 i/of k ce1 s dq0 dq10 v cc fv cc s dq12 dq7 gnd l dq8 dq2 dq11 nc dq5 dq14 mncncnc ncnc ncncnc nncncnc ncncnc pncncnc ncncnc
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? operation (1,3) ce ce ce ce ce f ce ce ce ce ce 1s ce2s oe oe oe oe oe we we we we we sa (6) lb lb lb lb lb s ub ub ub ub ub sdq 0- dq 7 dq 8 -dq 15 reset reset reset reset reset wp wp wp wp wp /acc (5) full standby h h x x x x x x high-z high-z h x h x l x x x x x high-z high-z h x output disable h l h h h x x x high-z high-z h x h l h x x x h h high-z high-z h x l h x h h x x x high-z high-z h x l x l h h x x x high-z high-z h x read from flash (2) lhxlhxxx d out d out hx lxl lhxxx d out d out hx write to flash l h x h l x x x d in d in hx lxlhlxxx d in d in hx read from sram h l h l h x l l d out d out hx h l h l h x h l high-z d out hx hlhlhxlhd out high-z h x write to sram h l h x l x l l d in d in hx h l h x l x h l high-z d in hx hlhxlxlh d in high-z h x temporary sector xxxxxxxx x x v id (8) x group unprotection (4) flash hardware x h x x x x x x high-z high-z l x reset x x l x x x x x high-z high-z l x boot block sector xxxxxxxx x x x l write protection notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. sa: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. device bus operations user bus operations (flash = word mode: i/of = vccf, sram = x16 version)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? notes: 1. any operations not indicated this column are inhibited.. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. sa: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. device bus operations operation ( 1,3) ce ce ce ce ce f ce1 ce1 ce1 ce1 ce1 s ce2s dq 15 /a-1 oe oe oe oe oe we we we we we sa (6) lb lb lb lb lb s ub ub ub ub ub s dq 0- dq 7 dq 8 -dq 15 reset reset reset reset reset wp/acc (5) full standby h h x x x x x x x high-z high-z h x h x l x x x x x x high-z high-z h x output disable h l h x h h x x x high-z high-z h x h l h x x x x h h high-z high-z h x l h x a-1 h h x x x high-z high-z h x l x l a-1 h h x x x high-z high-z h x read from flash (2) l h x a-1 l h x x x d out d out hx l x l a-1 l h x x x d out d out hx write to flash l h x a-1 h l x x x d in d in hx l x l a-1 h l x x x d in d in hx read from sram h l h x l h x l l d out d out hx h l h x l h x h l high-z d out hx hl h x lhxlhd out high-z h x write to sram h l h x x l x l l d in d in hx h l h x x l x h l high-z d in hx hl h x xlxlh d in high-z h x temporary sector x x x x x x x x x x x v id (8) x group unprotection (4) flash hardware x h x x x x x x x high-z high-z l x reset x x l x x x x x x high-z high-z l x boot block sector x x x x x x x x x x x x l write protection user bus operations (flash = byte mode: i/of = gnd, sram = x16 version)
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? device bus operations user bus operations (flash = word mode: i/of = vccf, sram = x8 version) notes: 1. any operations not indicated this column are inhibited.. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. lb s, ub s: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. operation (1,3) ce ce ce ce ce f ce ce ce ce ce 1s ce2s oe oe oe oe oe we we we we we sa lb lb lb lb lb s (6) ub ub ub ub ub s (6) dq 0- dq 7 dq 8 -dq 15 reset reset reset reset reset wp wp wp wp wp /acc (5) full standby h h x x x x x x high-z high-z h x h x l x x x x x high-z high-z h x output disable h l h h h x x x high-z high-z h x h l h x x x h h high-z high-z h x l h x h h x x x high-z high-z h x l x l h h x x x high-z high-z h x read from flash (2) lhxlhxxx d out d out hx lxl lhxxx d out d out hx write to flash l h x h l x x x d in d in hx lxlhlxxx d in d in hx read from sram h l h l h sa x x d out high-z h x write to sram h l h x l sa x x d in high-z h x temporary sector xxxxxxxx x x v id (8) x group unprotection (4) flash hardware x h x x x x x x high-z high-z l x reset x x l x x x x x high-z high-z l x boot block sector xxxxxxxx x x x l write protection
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. lb s, ub s: don?t care or open. 7. l = vil, h = vih, x = vil or vih. 8. see dc characteristics. device bus operations user bus operations (flash = byte mode: i/of = gnd, sram = x8 version) operation ( 1,3) ce ce ce ce ce f ce1 ce1 ce1 ce1 ce1 s ce2s dq 15 /a-1 oe oe oe oe oe we we we we we sa lb lb lb lb lb s (6) ub ub ub ub ub s (6) dq 0- dq 7 dq 8 -dq 15 reset reset reset reset reset wp/acc (5) full standby h h x x x x x x x high-z high-z h x h x l x x x x x x high-z high-z h x output disable h l h x h h x x x high-z high-z h x h l h x x x x h h high-z high-z h x l h x a-1 h h x x x high-z high-z h x l x l a-1 h h x x x high-z high-z h x read from flash (2) l h x a-1 l h x x x d out d out hx l x l a-1 l h x x x d out d out hx write to flash l h x a-1 h l x x x d in d in hx l x l a-1 h l x x x d in d in hx read from sram h l h x l h sa x x d out high-z h x write to sram h l h x x l sa x x d in high-z h x temporary sector x x x x x x x x x x x v id (8) x group unprotection (4) flash hardware x h x x x x x x x high-z high-z l x reset x x l x x x x x x high-z high-z l x boot block sector x x x x x x x x x x x x l write protection
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash - sector address sector address sector size (x8) (x16) bank sector a21-a12 kb/kw address range address range bank 1 sa0 0000000000 8/4 000000h?001fffh 00000h?00fffh bank 1 sa1 0000000001 8/4 002000h?003fffh 01000h?01fffh bank 1 sa2 0000000010 8/4 004000h?005fffh 02000h?02fffh bank 1 sa3 0000000011 8/4 006000h?007fffh 03000h?03fffh bank 1 sa4 0000000100 8/4 008000h?009fffh 04000h?04fffh bank 1 sa5 0000000101 8/4 00a000h?00bfffh 05000h?05fffh bank 1 sa6 0000000110 8/4 00c000h?00dfffh 06000h?06fffh bank 1 sa7 0000000111 8/4 00e000h?00fffffh 07000h?07fffh bank 1 sa8 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh bank 1 sa9 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh bank 1 sa10 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh bank 1 sa11 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh bank 1 sa12 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh bank 1 sa13 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh bank 1 sa14 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh bank 1 sa15 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh bank 1 sa16 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh bank 1 sa17 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh bank 1 sa18 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh bank 1 sa19 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh bank 1 sa20 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh bank 1 sa21 0001110xxx 64/32 0e0000h?0effffh 70000h?77fffh bank 1 sa22 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh bank 2 sa23 0010000xxx 64/32 100000h?00ffffh 80000h?87fffh bank 2 sa24 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh bank 2 sa25 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh bank 2 sa26 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh bank 2 sa27 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh bank 2 sa28 0010101xxx 64/32 150000h?15ffffh a8000h?affffh bank 2 sa29 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh bank 2 sa30 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh bank 2 sa31 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh bank 2 sa32 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh bank 2 sa33 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh bank 2 sa34 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh bank 2 sa35 0011100xxx 64/32 1c0000h?1cffffh e0000h?e7fffh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash - sector address continued: sector address sector size (x8) (x16) bank sector a21-a12 kb/kw address range address range bank 2 sa36 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh bank 2 sa37 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh bank 2 sa38 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh bank 2 sa39 0100000xxx 64/32 200000h?20ffffh f9000h?107fffh bank 2 sa40 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh bank 2 sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh bank 2 sa42 0100011xxx 64/32 230000h?23ffffh 118000h?11ffffh bank 2 sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh bank 2 sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh bank 2 sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh bank 2 sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh bank 2 sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh bank 2 sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh bank 2 sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh bank 2 sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh bank 2 sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh bank 2 sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh bank 2 sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh bank 2 sa54 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh bank 2 sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh bank 2 sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh bank 2 sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh bank 2 sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh bank 2 sa59 0110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh bank 2 sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh bank 2 sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh bank 2 sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh bank 2 sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh bank 2 sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh bank 2 sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh bank 2 sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh bank 2 sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh bank 2 sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh bank 2 sa69 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh bank 2 sa70 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sector address sector size (x8) (x16) bank sector a21-a12 kb/kw address range address range bank 3 sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh bank 3 sa72 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh bank 3 sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh bank 3 sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh bank 3 sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh bank 3 sa76 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh bank 3 sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh bank 3 sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh bank 3 sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh bank 3 sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh bank 3 sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh bank 3 sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh bank 3 sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh bank 3 sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh bank 3 sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh bank 3 sa86 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh bank 3 sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh bank 3 sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh bank 3 sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh bank 3 sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh bank 3 sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh bank 3 sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh bank 3 sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh bank 3 sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh bank 3 sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh bank 3 sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh bank 3 sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh bank 3 sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh bank 3 sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh bank 3 sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh bank 3 sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh bank 3 sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh bank 3 sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh bank 3 sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh bank 3 sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh flash - sector address continued:
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sector address sector size (x8) (x16) bank sector a21-a12 kb/kw address range address range bank 3 sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh bank 3 sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh bank 3 sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh bank 3 sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh bank 3 sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh bank 3 sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh bank 3 sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh bank 3 sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh bank 3 sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh bank 3 sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh bank 3 sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh bank 3 sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh bank 3 sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh bank 4 sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh bank 4 sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh bank 4 sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh bank 4 sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh bank 4 sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh bank 4 sa124 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh bank 4 sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh bank 4 sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh bank 4 sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh bank 4 sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh bank 4 sa129 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh bank 4 sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh bank 4 sa131 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh bank 4 sa132 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh bank 4 sa133 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh bank 4 sa134 1111111000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh bank 4 sa135 1111111001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh bank 4 sa136 1111111010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh bank 4 sa137 1111111011 8/4 7f6000h?7f7fffh 3fb000h?3fbfffh bank 4 sa138 1111111100 8/4 7f8000h?7f9fffh 3fc000h?3fcfffh bank 4 sa139 1111111101 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh bank 4 sa140 1111111110 8/4 7fc000h?7fdfffh 3fe000h?3fefffh bank 4 sa141 1111111111 8/4 7fe000h?7fffffh 3ff000h?3fffffh flash - sector address continued: note: the address range is a21:a-1 in byte mode (i/of=vil) or a21:a0 in word mode (i/of=vih). the bank address bits are a21 - a19.
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sector group address sector group a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 sectors sga0 0 0 0 0 0 0 0 0 0 0 sa0 sga1 0 0 0 0 0 0 0 0 0 1 sa1 sga2 0 0 0 0 0 0 0 0 1 0 sa2 sga3 0 0 0 0 0 0 0 0 1 1 sa3 sga4 0 0 0 0 0 0 0 1 0 0 sa4 sga5 0 0 0 0 0 0 0 1 0 1 sa5 sga6 0 0 0 0 0 0 0 1 1 0 sa6 sga7 0 0 0 0 0 0 0 1 1 1 sa7 01 sga8 0 0 0 0 0 1 0 x x x sa8 to sa10 11 sga9 0 0 0 0 1 x x x x x sa11 to sa14 sga10 0 0 0 1 0 x x x x x sa15 to sa18 sga11 0 0 0 1 1 x x x x x sa19 to sa22 sga12 0 0 1 0 0 x x x x x sa23 to sa26 sga13 0 0 1 0 1 x x x x x sa27 to sa30 sga14 0 0 1 1 0 x x x x x sa31 to sa34 sga15 0 0 1 1 1 x x x x x sa35 to sa38 sga16 0 1 0 0 0 x x x x x sa39 to sa42 sga17 0 1 0 0 1 x x x x x sa43 to sa46 sga18 0 1 0 1 0 x x x x x sa47 to sa50 sga19 0 1 0 1 1 x x x x x sa51 to sa54 sga20 0 1 1 0 0 x x x x x sa55 to sa58 sga21 0 1 1 0 1 x x x x x sa59 to sa62 sga22 0 1 1 1 0 x x x x x sa63 to sa66 sga23 0 1 1 1 1 x x x x x sa67 to sa70 sga24 1 0 0 0 0 x x x x x sa71 to sa74 sga25 1 0 0 0 1 x x x x x sa75 to sa78 sector address size (x8) (x16) a21-a12 byte / word address range address range 0000000xxx 256/128 00000h-0000ffh 00000h-0007fh flash - security sector addresses (hidden-rom)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sector group a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 sectors sga26 1 0 0 1 0 x x x x x sa79 to sa82 sga27 1 0 0 1 1 x x x x x sa83 to sa86 sga28 1 0 1 0 0 x x x x x sa87 to sa90 sga29 1 0 1 0 1 x x x x x sa91 to sa94 sga30 1 0 1 1 0 x x x x x sa95 to sa98 sga31 1 0 1 1 1 x x x x x sa99 to sa102 sga32 1 1 0 0 0 x x x x x sa103 to sa106 sga33 1 1 0 0 1 x x x x x sa107 to sa110 sga34 1 1 0 1 0 x x x x x sa111 to sa114 sga35 1 1 0 1 1 x x x x x sa115 to sa118 sga36 1 1 1 0 0 x x x x x sa119 to sa122 sga37 1 1 1 0 1 x x x x x sa123 to sa126 sga38 1 1 1 1 0 x x x x x sa127 to sa130 00 sga39 1 1 1 1 1 0 1 x x x sa131 to sa133 10 sga40 1 1 1 1 1 1 1 0 0 0 sa134 sga41 1 1 1 1 1 1 1 0 0 1 sa135 sga42 1 1 1 1 1 1 1 0 1 0 sa136 sga43 1 1 1 1 1 1 1 0 1 1 sa137 sga44 1 1 1 1 1 1 1 1 0 0 sa138 sga45 1 1 1 1 1 1 1 1 0 1 sa139 sga46 1 1 1 1 1 1 1 1 1 0 sa140 sga47 1 1 1 1 1 1 1 1 1 1 sa141 sector group address continued:
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 a -1 (1) code (hex) manufacturer?s code ba vil vil vil vil vil vil 04h device code byte ba vil vil vil vil vih vil 7eh word ba vil vil vil vil vih x 227eh extended device code (3) byte ba vil vih vih vih vil vil 02h word ba vil vih vih vih vil x 2202h extended device code (3) byte ba vil vih vih vih vih vil 01h word ba vil vih vih vih vih x 2201h sector group protection sector group vil vil vil vih vil vil 01h (2) addresses flash memory autoselect codes note: 1. a?1 is used for byte mode. 2. outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. 3. at word mode, a read cycle at address (ba) 01h (at byte mode, (ba) 02h) outputs device code. when 227eh (at byte mode, 7eh) was output, this indicates that there will require two additional codes, called extended device codes. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh (at byte mode, (ba) 1ch) , as well as at (ba) 0fh (at byte mode, (ba) 1eh) .
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash memory command definitions command sequence bus 6 1 1 3 2 2 4 1 3 4 6 4 bus write cycle req'd first bus second bus third bus fourth bus fifth bus sixth bus cycle write cycle write cycle read/write cycle cycle ? pa data read / reset * 1 hidden-rom exit * 5 extended sector group protection * 3 set to fast mode fast program * 2 data data 2aah 555h ? addr. addr. xxxh ba ba 555h aah ? addr. addr. data ? addr. data ? addr. ? ? ? data read / reset ? pa spa xxxh ? 60h f0h*6 ? spa ? ? pa ? ? spa ? ? ? ? ? ? ra ? ? ? ? ? ? ? ? ? ? 55h ? ? ? ? ? ? ? ? ? ? ? ? hra 555h aaah sa ? ? ? ? ? ? ? ? ? 30h 10h ? ? ? 30h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 55h 55h 55h 55h 55h ? ? 55h pd f0h aah aah aah aah f0h ? ? rd ? aah pd aah ? ? ? ? ? sd ? ? pd aah 00h a0h 80h 80h ? ? 20h ? ? 40h ? 88h a0h 80h 90h aah b0h 30h ? 555h aaah ? ? xxxh ba xxxh aah a0h 90h 60h 98h aah aah aah aah 55h 55h 55h 55h word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte word byte 55h aah 555h aaah 555h aaah 555h aaah 555h aaah 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 2aah 555h 555h 555h aaah 555h aaah 555h aaah 555h aaah 555h aaah 555h aaah 555h (hrba) 2aah 555h 2aah 555h 2aah 555h 555h aaah 555h aaah 555h aaah xxxh reset from fast mode * 2 555h aaah 555h aaah 555h aaah 555h aaah 555h aaah autoselect program chip erase sector erase sector erase suspend sector erase resume query * 4 hidden-rom entry hidden-rom program * 5 hidden-rom erase * 5 90h ? ? 55h 55h ? (ba) aaah (hrba) aaah 555h aaah 1 3 3 4 (ba) note: *1: both read/reset commands are functionally equivalent, resetting the device to the read mode. *2: this command is valid during fast mode. *3: this command is valid while reset=vid. *4: the valid address is a0 to a6. *5: this command is valid during hi-rom mode. *6: the data ?00h? is also acceptable.
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? mcp absolute maximum ratings (1,2,3) symbol parameter value unit t bias temperature under bias ?40 to +85 c t stg storage temperature ?55 to +125 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for data, ?0.3 to v cc f + 0.3 v address and control pins -0.2 to v cc s + 0.3 v v in reset (5) -0.5 to +13.0 v v in wp /acc (6) -0.5 to +10.5 v v cc f/v cc s voltage on vcc supply relatiive to gnd (4) ?0.3 to 3.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 4. minimum dc voltage on input or i/o pins is ?0.3 v. during voltage transitions, input or i/o pins may undershoot vss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f+0.3 v or v cc s+0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f+2.0 v or v cc s+2.0 v for periods of up to 20 ns. 5. minimum dc input voltage on reset pin is ?0.5 v. during voltage transitions, reset pin may undershoot vss to ?2.0 v for per iods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc f or v cc s) does not exceed 9.0 v. maximum dc input voltage on reset pin is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. 6. minimum dc input voltage on wp /acc pin is ?0.5 v. during voltage transitions, wp /acc pin may undershoot vss to ?2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0v for periods of up to 20 ns, when v cc f is applied. flash memory command definitions continued: hra= address of the hidden-rom area word mode: 000000h to 00007fh byte mode: 000000h to 0000ffh hrba = bank address of the hidden-rom area a21 = a20 = a19 = 0 rd = data read from location ra during read operation. pd = data to be programmed at location pa. sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. the system should generate the following address patterns; word mode : 555h or 2aah to addresses a0 to a10 byte mode : aaah or 555h to addresses a?1 and a0 to a10 a ddress bits a21 to a11 = x = ?h? or ?l? for all address commands except for program address (pa), sector address (sa),and bank address (ba). bus operations are defined in ?device bus operations?. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a21, a20, a19, a18, a17, a16, a15, a14, a13, and a12 will uniquely select any sector. ba = bank address (a21 to a19 ) spa = sector group address to be protected. set sector group address (sga) and (a6, a3, a2, a1, a0) = (0, 0, 0,1, 0) for protect; or sga and (a6, a3, a2, a1, a0) = (1, 0, 0,1, 0) for unprotect.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? mcp operating range range ambient temperature v ccf ,v ccs industrial ?40c to +85c 2.7?3.3v capacitance (1) symbol parameter conditions typ. max. unit c in input capacitance v in = 0v 11 14 pf c out output capacitance v out = 0v 12 16 pf c in 2 control pin capacitance v in = 0v 14 16 pf c in 3 wp /acc pin capacitance v in = 0v 21.5 26 pf notes: 1. test conditions: t a = 25c, f = 1 mhz standard voltage range v cc = 2.7-3.3 v f lash m emory sram u nits max access time 70 85 70 ns ce access 70 85 70 ns oe access 30 40 35 ns
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? symbol parameter test conditions min. max. unit i li input leakage v in =v ss to v cc f, v cc s -1.0 1.0 a i lo output leakage v out =v ss to v cc f, v cc s -1.0 1.0 a v il input low level -0.2 0.5 v v ih input high level 2.4 v cc + 0.3 (2) v v id voltage for sector 11.5 12.5 v protection, and temporary sector unprotection ( reset ) (1) v acc voltage for program 8.5 9.5 v acceleration ( wp /a cc ) (1) v ol output low level v cc f = v cc f min., v ccs =v ccs min. ? 0.4 v i ol = 1.0ma v oh output high level v cc f = v cc f min., v ccs =v ccs min. 2.4 ? v i oh = -0.5ma v lko flash low vccf 2.3 2.5 v mcp dc characteristics notes: 1. applicable for only v cc f applying. 2. v cc indicates lower of v cc f or v cc s .
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash dc characteristics symbol parameter test conditions min. max. unit i lit reset inputs v cc f=v cc f max., v cc s=v cc s max. ? 35 a leakage current reset = 12.5v i lia acc inputs v cc f=v cc f max., v cc s=v cc s max. ? 20 a leakage current wp /acc = vacc max. i cc 1f flash vcc (1) ce f=v il tcycle = 5mhz byte ? 16 ma active current (read) oe =v ih tcycle = 5mhz word ? 18 tcycle = 1mhz byte ? 7 tcycle = 1mhz word ? 7 i cc 2f flash vcc active (2) ce f=v il ?35ma current(program/erase) oe =v ih i cc 3f flash vcc active (4) ce f=v il byte ? 51 ma current oe =v ih word 53 (read-while-program) i cc 4f flash vcc active (4) ce f=v il byte ? 51 ma current oe =v ih word 53 (read-while-erase) i cc 5f flash vcc active ce f=v il ?35ma current oe =v ih (erase-suspend-program) i sb 1f flash vcc v cc f = vcc max, ce f= v cc f = + 0.3v ? 5 a standby current reset, ce f, wp /acc = v cc f = + 0.3v i sb 2f flash vcc v cc f = vcc max, reset = v ss = + 0.3v ? 5 a standby current wp /acc = v cc f = + 0.3v ( reset ) i sb 3f flash vcc (3) v cc f = vcc max. ce f, = v ss = + 0.3v ? 5 a standby current reset, wp /acc = v cc f = + 0.3v (auto sleep mode) v in = v cc f + 0.3v or v ss + 0.3v notes: 1. the icc current listed includes both the dc operating current and the frequency dependent component. 2. icc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns.. 4. embedded algorithm (program or erase) is in progress. (@5 mhz)
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? timing diagram for alternating sram to flash cef ce1 s ce2s t ccr t ccr t ccr t ccr t chold t chold we jedec standard parameter symbol symbol condition min unit ce recover time ? t ccr ?0ns ce hold time ? t chold ?3ns ac characteristics - ce ce ce ce ce timing
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash read only switching characteristics (over operating range) symbol parameter min. max. min. max. unit t rc cycle time 70 85 ? ns t acc address to output delay ? 70 ? 85 ns t ce chip enable to output delay ? 70 ? 85 ns t oe output enable to output delay ? 30 ? 40 ns t df chip enable to output high-z ? 30 ? 30 ns t df output enable to output high-z ? 30 ? 30 ns t oh output hold time from addresses, 0 ? 0 ? ns ce f or oe , whichever occurs first t ready reset pin low to read mode ? 20 ? 20 s flash ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 5 ns input and output timing 1.5v and reference level output load 1 ttl gate and 30pf
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash read cycle address dq cef oe we address stable output valid high-z high-z t oeh t rc t oe t df t ce t acc t oh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash hardware reset reset reset reset reset / read operation timing diagram address dq cef reset address stable output valid high-z t rc t acc t rh t ce t rh t rp t oh
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? note: 1. this reflects typcial value not maximum value and does not include the preprogramming time. flash erase/program operation characteristics (over operating range) -70 ns -85ns symbol parameter min. max. min. max. unit t wc write cycle time 70 - 85 - ns t as address setup time ( we to addr.) 0 - 0 - ns t aso address setup time to ce f low during 15 - 15 - ns toggle bit polling t ah address hold time ( we to addr.) 45 - 45 - ns t aht address hold time from ce f or 0 - 0 - ns oe high during toggle bit polling t ds data setup time 35 - 45 - ns t dh data hold time 0 - 0 - ns t oes output enable setup time 0 - 0 - ns t oeh output enable hold time read 0 - 0 - ns t oeh output enable hold time 10 - 10 - ns toggle and data polling t ceph ce f high during toggle bit polling 20 - 20 - ns t oeph oe high during toggle bit polling 20 - 20 - ns t ghel read recover time before write ( oe to ce f) 0 - 0 - ns t ghwl read recover time before write ( oe to we )0-0-ns t ws we setup time (cef to we) 0 - 0 - ns t cs ce f setup time (we to cef) 0 - 0 - ns t wh we hold time (cef to we) 0 - 0 - ns t ch ce f hold time (we to cef) 0 - 0 - ns t wp write pulse width 30 - 35 - ns t cp ce f pulse width 30 - 35 - ns t wph write pulse width high 30 - 30 - ns t cph ce f pulse width high 30 - 30 - ns t whwh 1 byte programming operation - 12 - 15 s t whwh 1 word programming operation - 15 - 20 s t whwh 2 sector erase operation (1) -0.7 - 1 s t vcs v cc f setup time 50 - 50 - s
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? note: 2. this timing is for sector protection operation. 3. the time between writes must be less than ?ttow ? otherwise that command will not be accepted and erasure will start. a time-out or ?ttow ? from the rising edge of last ce f or we whichever happens first will initiate the execution of the sector erase command(s). 4. when the erase suspend command is written during the sector erase operation, the device will take a maximum of ?tspd ? to suspend the erase operation. flash erase/program operation characteristics continued (over operating range) -70 ns -85ns symbol parameter min. max. min. max. unit t vlht voltage transition time (2) 4- 4 - s t vidr rise time to v id (2) 500 - 500 - ns t vacca rise time to v acc 500 - 500 - ns t rb recovery time from ry/ by 0- 0 - ns t rp reset pulse width 500 - 500 - ns t eoe delay time from embedded output enable - 70 - 85 ns t rh reset high level period before read 100 - 200 - ns t busy program/erase valid to ry/b y delay - 75 - 90 ns t tow erase time-out time (3) 50 - 50 - s t spd erase suspend transition time (4) - 20 -20 s
28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash write cycle ( we control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode (the addresses differ from 8 mode, i.e. aaah). address dq cef oe we a0h dq 7 dout pa 555h pa data p pd dt t as 3rd bus cycle t sh t wc t rc t oe t ce t oh t df t ds t dh t whwh1 t cs t ch t ghwl t wp t wph
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash write cycle ( ce f control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode (the addresses differ from 8 mode, i.e. aaah). address dq cef oe we a0h dq 7 dout pa 555h pa data p pd t as 3rd bus cycle t ah t wc t ds t dh t whwh1 t ws t wh t ghel t cp t cph
30 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash ac waveforms chip/sector erase operations *sa is the sector address for sector erase. address = 555h for chip erase. note: these waveforms are for the 16 mode (the addresses differ from 8 mode: aaah, 555h, aaah, aaah, 555h, sa*). address dq cef oe we 55h 10h/ 30h vccf 55h aah 80h aah 555h 2aah 555h 555h 2aah sa* 30h for sector erase t wc t as t ah t cs t ch t wp t wph t vcs t ghwl t ds t dh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash ac waveforms for data polling during embedded alogrithm operations *dq7 = valid data (the device has completed the embedded operation.) data in dq 0 /dq 6 cef oe we ry/ by dq data in dq 7 dq0 to dq6 = output flag dq0 to dq6 valid data dq7 = valid data t df t busy t whwh1 or 2 t oe t eoe t oeh t cef t ch high - z high - z
32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash ac waveforms for toggle bit during embedded algorithm operations * dq6 stops toggling (the device has completed the embedded operation). toggle toggle toggle toggle outpu t data data data data valid data address dq 6 /dq 2 cef oe we t dh t busy t oeh t oe ry/ by t cef * t oeh t oeph t ceph t aht t aso t aht t as
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 33 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash back-to-back read/write timing diagram note: this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2. address dq cef oe we ba1 ba1 ba1 t rc t as t ah t acc t ce ba2 (555h) ba2 (pa) ba2 (pa) read command read command read read valid valid valid valid valid output input output input output status t wc t rc t wc t rc t rc t ds t dh t df t df t oeh (pd) t ghwl t wp (a0h) t oe t ceph t aht t as
34 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash ry/ by by by by by timing diagram during write/erase operations flash reset reset reset reset reset ry/ by by by by by timing diagram we cef ry/ by the rising edge of the last we signal entire programming or erase operations t busy we reset ry/ by t ready t rp t rb
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 35 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash temporary sector group unprotection reset v ccf v id v ih cef we ry /by program or erase command sequence unprotection period vidr t vcs t vlht t vlht t vlht
36 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash accelerated program wp/ acc vccf vacc vih cef we ry /by acceleration period t vaccr t vcs t vlht t vlht t vlht program command sequence
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 37 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? flash extended sector group protection sgax: sector group address to be protected. sgay: next group sector address to be protected unprotection: implement with a6 = 1, a1 = 1, a0 = 0. time-out approximately 15 ms. time-out : time-out window = 250 s (min.) reset address a3, a2, a0 a1 a6 cef oe we data vccf 60h 60h 40h 01h 60h sgax sgay sgax time-out t vcs vidr vlht t wc t wp t oe t wc
38 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sram power supply characteristics (1) (over operating range) symbol parameter test conditions min. max. unit i cc vcc dynamic operating v ccs = max., ? 25 ma supply current i out = 0 ma, f = f max i cc 1 operating supply v ccs = max., ? 5 ma current i out = 0 ma, f = 0 i sb 1 ttl standby current v ccs = max., ? 0.3 ma (ttl inputs) v in = v ih or v il ce1 s = v ih , ce2 s = v il , f = 1 mh z or ulb control v ccs = max., v in = v ih or v il ce1 s = v il , f = 0, ub s = v ih , lb s = v ih i sb 2 cmos standby v ccs = max., ? 25 a current (cmos inputs) ce1 s v ccs ? 0.2v, ce2 s 0.2v, v in v ccs ? 0.2v, or v in 0.2v, f = 0 or ulb control v ccs = max., ce1 s = v il v in 0.2v, f = 0; ub s / lb s = v ccs ? 0.2v note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 39 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sram ac test conditions parameter unit input pulse level 0.4v to vcc - 0.3v input rise and fall times 5 ns input and output timing 1.5v and reference level output load 1 ttl gate and 30pf sram read cycle switching characteristics (1) (over operating range) 70 ns symbol parameter min. max. unit t rc read cycle time 70 ? ns t aa address access time ? 70 ns t oha output hold time 10 ? ns t ace1 ce1 s access time ? 70 ns t doe oe access time ? 35 ns t hzoe (2) oe to high-z output ? 25 ns t lzoe (2) oe to low-z output 5 ? ns t hzce1 (2) ce1 s to high-z output 0 25 ns t lzce1 (2) ce1 s to low-z output 10 ? ns t ba lb s , ub s access time ? 70 ns t hzb lb s , ub s to high-z output 0 25 ns t lzb lb s , ub s to low-z output 0 ? ns notes: 1. see sram ac test conditions. 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
40 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? ac waveforms sram read cycle no. 1 (1,2) (address controlled) ( ce1 s = oe = v il , ub ub ub ub ub s or lb lb lb lb lb s = v il ) ac waveforms sram read cycle no. 2 (1,3) ( ce1 s , oe , and ub s / lb s controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce1 , ub s , or lb s = v il . 3. address is valid prior to or coincident with ce1 low transition. data valid previous data valid t aa t oha t oha t rc dout address t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzce1 address oe ce1 s ce2 s dout lb s , ub s t hzb t ba t lzb
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 41 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? write cycle switching characteristics (1) (over operating range) 70 ns symbol parameter min. max. unit t wc write cycle time 70 ? ns t sce1 ce1 s to write end 60 ? ns t aw address setup time to write end 60 ? ns t ha address hold from write end 0 ? ns t sa address setup time 0 ? ns t pwb lb s , ub s valid to end of write 60 ? ns t pwe we pulse width 50 ? ns t sd data setup to write end 30 ? ns t hd data hold from write end 0 ? ns t hzwe (2) we low to high-z output ? 20 ns t lzwe (2) we high to low-z output 5 ? ns notes: 1. see sram ac test conditions. 2. transition is measured 500 mv from steady-state voltage. notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce1 s and we inputs and at least one of the lb s and ub s inputs being in the low state. 2. write = ( ce1 s ) [ ( lb s ) = ( ub s ) ] ( we ). ac waveforms sram write cycle no. 1 (1,2) ( ce1 ce1 ce1 ce1 ce1 s controlled, oe = high or low) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe (4) t hzwe high-z t lzwe t sa t sd t hd address ce1 s ce2 s we dout din lb s , ub s
42 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sram write cycle no. 2 ( we controlled: oe is high during write cycle) sram write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe1, 2 t hzwe high-z t lzwe t sa t sd t hd address oe ce1s ce2s we lbs , ubs dout din data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe1, 2 t hzwe high-z t lzwe t sa t sd t hd address oe ce1s ce2s we lbs , ubs dout din
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 43 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? sram data retention switching characteristics symbol parameter test condition min. max. unit v dr vcc for data retention see data retention waveform 1.0 3.3 v i dr data retention current vcc = 1.0v, cs1 vcc ? 0.2v ? 15 a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns sram data retention waveform ( ce1 controlled) write cycle no. 4 ( ub s / lb s controlled, ce1 s is low, ce2s is high) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe (4) t hzwe high-z t lzwe t sa t sd t hd address ce1 s ce2 s we dout din lb s , ub s v cc ce1 s v cc - 0.2v t sdr t rdr v dr ce1 s gnd 2.7v 2.5v data retention mode
44 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k l m a b c d e f g h j k l m ? 0.45 + 0.10/?0.05 (73x) d e e a1 seating plane a d1 e1 e symbol min. typ. max. units a? ?1.40mm a1 0.28 0.38 0.48 mm d 11.50 11.60 11.70 mm d1 ? 8.80 ? mm e 7.90 8.00 8.10 mm e1 ? 7.20 ? mm e ? 0.80 ? mm mini ball grid array ? 73-ball bga package code: b ( 8.00 mm x 11.60 mm body, 0.8 mm ball pitch )
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 45 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? mini ball grid array ? 101-ball bga (64 mb flash and 8 mb sram) package code: a ( 11 mm x 12 mm body, 0.8 mm ball pitch ) symbol min. typ. max. units a? ?1.40mm a1 0.28 0.38 0.48 mm d 11.90 12.00 12.10 mm d1 ? 10.40 ? mm e 10.90 11.00 11.10 mm e1 ? 8.80 ? mm e ? 0.80 ? mm 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m n p a b c d e f g h j k l m n p ? 0.45 + 0.10/?0.05 (101x) e e a1 seating plane e dd1 e1 a
46 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? is 71 x xx f xx x s xx ? xxxx x x flash organization : a = type a - top boot block (bank1: 4mbit, bank2: 28mbit) b = type b - top boot block (bank1: 8mbit, bank2: 24mbit) c = type c - top boot block (bank1: 16mbit, bank2: 16mbit) d = type d - bottom boot block (bank1: 4mbit, bank2: 28mbit) e = type e - bottom boot block (bank1: 8mbit, bank2: 24mbit) f = type f - bottom boot block (bank1: 16mbit, bank2: 16mbit) g = user configurable bank grouping h = type h - top boot block (bank1: 0.5mbit, bank2: 15.5mbit) j = type j - top boot block (bank1: 2mbit, bank2: 14mbit) k = type k - top boot block (bank1: 4mbit, bank2: 12mbit) l = type l - top boot block (bank1: 8mbit, bank2: 8mbit) m = type m - bottom boot block (bank1: 0.5mbit, bank2: 15.5mbit) n = type n - bottom boot block (bank1: 2mbit, bank2: 14mbit) p = type p - bottom boot block (bank1: 4mbit, bank2: 12mbit) q = type q - bottom boot block (bank1: 8mbit, bank2: 8mbit) temperature grade: blank = commercial i = industrial package: a = 101-ball bga b = 73-ball bga f = 69-ball bga speed : 8570 = 85ns flash, 70ns sram 7070 = 70ns flash, 70ns sram 8585 = 85ns flash, 85ns sram 7085 = 70ns flash, 85ns sram sram density (mbit) sram label issi prefix product family: flash/sram mcp voltage : v = 3.0 center voltage sram data bus width: 08, 16, or pc (pin configurable) flash label flash density (mbit) part number logic
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 47 preliminary information rev. 00c 07/22/02 is71v08f64gs08, is71v16f64gs08 issi ? ordering information industrial range: -40oc to +85oc sram flash bank flash sram order part no. data bus organization speed(ns) speed(ns) package is71v08f64gs08-7070bi 8 user configurable 70 70 73-ball bga is71v08f64gs08-7085bi 8 user configurable 70 85 73-ball bga is71v08f64gs08-8570bi 8 user configurable 85 70 73-ball bga is71v08f64gs08-8585bi 8 user configurable 85 85 73-ball bga is71v16f64gs08-7070bi 16 user configurable 70 70 73-ball bga is71v16f64gs08-7085bi 16 user configurable 70 85 73-ball bga is71v16f64gs08-8570bi 16 user configurable 85 70 73-ball bga is71v16f64gs08-8585bi 16 user configurable 85 85 73-ball bga is71v08f64gs08-7070ai 8 user configurable 70 70 101-ball bga IS71V08F64GS08-7085AI 8 user configurable 70 85 101-ball bga is71v08f64gs08-8570ai 8 user configurable 85 70 101-ball bga is71v08f64gs08-8585ai 8 user configurable 85 85 101-ball bga is71v16f64gs08-7070ai 16 user configurable 70 70 101-ball bga is71v16f64gs08-7085ai 16 user configurable 70 85 101-ball bga is71v16f64gs08-8570ai 16 user configurable 85 70 101-ball bga is71v16f64gs08-8585ai 16 user configurable 85 85 101-ball bga

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